--------------------------------------------------------------------------------
-- Company: 			StrathSat-R	
-- Engineer:			Thomas Parry
--
-- Create Date:   	15:23:20 07/29/2012
-- Design Name:   
-- Module Name:   	/home/tom/VHDL/StrathSat-R/crc_gen/open_crc/cmd_tx_tb.vhd
-- Project Name:  	sd_host
-- Target Device:  	Spartan 6
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: cmd_tx
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY cmd_tx_tb IS
END cmd_tx_tb;
 
ARCHITECTURE behavior OF cmd_tx_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT cmd_tx
    PORT(
         Clk : IN  std_logic;
         Strobe : IN  std_logic;
         Cmd : IN  std_logic_vector(5 downto 0);
         Argument : IN  std_logic_vector(31 downto 0);
         Output : OUT  std_logic;
         Done : OUT  std_logic
        );
    END COMPONENT;
	 
    

   --Inputs
   signal Clk : std_logic := '0';
   signal Strobe : std_logic := '0';
   signal Cmd : std_logic_vector(5 downto 0) := (others => '0');
   signal Argument : std_logic_vector(31 downto 0) := (others => '0');

 	--Outputs
   signal Output : std_logic;
   signal Done : std_logic;

   -- Clock period definitions
   constant Clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: cmd_tx PORT MAP (
          Clk => Clk,
          Strobe => Strobe,
          Cmd => Cmd,
          Argument => Argument,
          Output => Output,
          Done => Done
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for Clk_period*10;

      -- insert stimulus here 
		Cmd 		<= (others => '0');
		Argument	<= (others => '0');
		Strobe	<= '1';
		
		wait for Clk_period;
		
		Strobe	<= '0';

      wait;
   end process;

END;
